An important trend of development in semiconductor technology is scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) for improving integration level and reducing manufacturing cost. However, it is well known that short channel effects arise as the size of MOSFETs decreases. As the MOSFETs are scaled down, a gate also has a reduced effective length and actually controls fewer charges in a depletion region when a gate voltage is applied. Consequently, a threshold voltage of the MOSFETs drops with a reduced channel length.
In the MOSFETs, it may be desirable on one hand that the threshold voltage of the device is increased to suppress the short channel effects, and on the other hand that the threshold voltage of the device is decreased to reduce power consumption in a low supply voltage application, or in an application using both P-type and N-type MOSFETs.
Channel doping is a known approach of tuning the threshold voltage. However, if the threshold voltage of the device is raised by increasing a doping concentration in a channel region, mobility of carriers drops, which results in degradation of the device performance. Moreover, ions with a high doping concentration in the channel region may neutralize ions in regions adjacent to source/drain regions and the channel region, which decreases a doping concentration in the adjacent region and increases resistance of the device.
The short channel effects can be suppressed by providing a ground plane (i.e. a grounded back gate) beneath a buried insulating layer. However, an integrated circuit may comprise many MOSFETs with different gate lengths. Although a high doping concentration in the back gate may be beneficial to the MOSFET with a short gate length for suppressing the short channel effects, it causes an excessively high threshold voltage for the MOSFET with a long gate length. Thus, it is desirable that the threshold voltage is adjusted differently for the MOSFETs with different gate lengths.
Moreover, in an SOI MOSFET, a back gate may be short-circuited to source/drain regions. In a conventional structure of the SOI MOSFET shown in FIG. 10, a back gate 18 is typically isolated from source/drain regions (not shown) in a semiconductor layer 13 by a buried insulating layer 12. However, the buried insulating layer 12 has only a thickness of about 5 nm-30 nm. A conductive path 22′ may be unintentionally formed between the back gate 18 and the source/drain regions during a source/drain doping process or a silicidation process. Moreover, a conductive path 24′ may be unintentionally formed between the back gate 18 and the source/drain regions in the process for providing conductive vias, due to misalignment when forming via holes by etching.
Thus, it is still desirable that the short circuit between the back gate and the source/drain regions can be avoided while the threshold voltage of the device is adjusted by the back gate.